Vlsi lab Viva questions1) Tell something about why we do gate level simulations?
2) Say if I perform Formal Verification say Logical Equivalence across Gatelevel netlists(Synthesis and post routed netlist). Do you still see a reason behind GLS.?
3)An AND gate and OR gate are given inputs X & 1 , what is expected output?
4) What is difference between NMOS & RNMOS?
5) Tell something about modeling delays in verilog?
6) With a specify block how to defining pin-to-pin delays for the module ?
7) What are conditional path delays?
8) Tell something about Rise, fall, and turn-off delays?
9) What is delay modeling timing checks?
10)What are the synthesizable gate level constructs?
11) What are the synthesizable gate level constructs?
12) What are Design Rule Check (DRC)?
13) What is Layout Vs Schematic (LVS) ?
14) What are steps involved in Semiconductor device fabrication ?
15) What is Clock distribution network ?
16) What is Clock Gating ?
17) What is Netlist ?
18)What Physical timing closure ?
19)What Physical verification ?
20)What is Stuck-at fault ?
21)What is Different Logic family ?
22)What is Different Types of IC packaging?
23)What is Substrate coupling ?
24)What is Latchup ?
25)What is Body effect ?
26)What are standard Cell's?
27)Why is NAND gate preferred over NOR gate for fabrication?
28)What is Noise Margin? Explain the procedure to determine Noise Margin
29)Explain sizing of the inverter?
30)How do you size NMOS and PMOS transistors to increase the threshold voltage?
31)What happens to delay if you increase load capacitance?
32)What happens to delay if we include a resistance at the output of a CMOS circuit?
33)What are the limitations in increasing the power supply to reduce delay?
34)How does Resistance of the metal lines vary with increasing thickness and increasing length?
35)For CMOS logic, give the various techniques you know to minimize power consumption?
36)What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus?
37)Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?
38)How do you avoid Latch Up?
39)What is Body Effect?
40)Give the expression for CMOS switching power dissipation?
41)Why is the substrate in NMOS connected to Ground and in PMOS to VDD?
42)What is the fundamental difference between a MOSFET and BJT ?
43)Which transistor has higher gain. BJT or MOS and why?
44)Why do we gradually increase the size of inverters in buffer design when trying to drive a high capacitive load?
45)All of us know how an inverter works. What happens when the PMOS and NMOS are interchanged with one another in an inverter?
46)Why PMOS and NMOS are sized equally in a Transmission Gates?
47)A good question on Layouts. Give 5 important Design techniques you would follow when doing a Layout for Digital Circuits?
48)What is metastability? When/why it will occur?Different ways to avoid this?
49)Let A and B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay of the two series NMOS inputs A and B which one would you place near to the output?
50)Write a verilog code to swap contents of two registers with and without a temporary register?
51)Tell me about verilog file I/O?
52)Difference between task and function?
53)Difference between inter statement and intra statement delay?
54)What is delta simulation time?
55)Difference between $monitor,$display & $strobe?
56)What is difference between Verilog full case and parallel case?
57)What is meant by inferring latches,how to avoid it?
58)Tell me how blocking and non blocking statements get executed?
59)Variable and signal which will be Updated first?
60)What is sensitivity list?
61)In a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk? if yes, why?
62)Tell me structure of Verilog code you follow?
63)Given only two xor gates one must function as buffer and another as inverter?
64)What is difference between latch and flipflop?
65)Tell some of applications of buffer?
66)Give two ways of converting a two input NAND gate to an inverter?
67)What are set up time & hold time constraints?
68)Differences between D-Latch and D flip-flop?
69)What is a multiplexer?
70)How can you convert an SR Flip-flop to a JK Flip-flop?
71)How can you convert the JK Flip-flop to a D Flip-flop?
72)What is Race-around problem?How can you rectify it?
73)Difference between Synchronous,Asynchronous & Isynchronous communication?
74)In a 3-bit Johnson's counter what are the unused states?
75)What is difference between setup and hold time?
76)How will you implement a Full subtractor from a Full adder?
77)7 bit ring counter's initial state is 0100010. After how many clock cycles will it return to the initial state?
78)How do you detect if two 8-bit signals are same?
79)What is Race-around problem?How can you rectify it?
80)How can you convert the JK Flip-flop to a D Flip-flop?
81)How can you convert an SR Flip-flop to a JK Flip-flop?
82)What is a multiplexer?
83)Differences between D-Latch and D flip-flop?
84)Give two ways of converting a two input NAND gate to an inverter?
85)Tell some of applications of buffer?
86)What is difference between latch and flipflop?
87)Given only two xor gates one must function as buffer and another as inverter?
88)How can I pass parameters to my simulation?
